1. Field of the Invention
The present invention relates to a phase selector and in particular to a commutating phase selector.
2. Description of the Related Art
Stable oscillations at different frequencies, which are needed in today's radio frequency (RF) transceivers, are typically generated using a phase-locked loop (PLL). FIG. 1 illustrates a simplified frequency synthesizer 100 that can generate different frequencies using a PLL. Specifically, in frequency synthesizer 100, a phase detector 101 can receive a reference frequency signal Fref and a low-frequency signal f(div). If these signals are equal in phase, then phase detector 101 would generate no output. On the other hand, if these signals are not in phase, then that difference can be converted to an output voltage.
A loop filter 102, which filters that output voltage, provides an output signal to a voltage-controlled oscillator (VCO) 103. In one embodiment, the characteristics of loop filter 102 can be selected to achieve minimum transition time between two frequencies, maximize suppression of reference sidebands in the output frequency spectrum, and minimize phase noise generated by the PLL.
VCO 103 can change its frequency based on the signal provided by loop filter 102. VCO 103 generates an output frequency Fout, which is provided to a prescaler 104. Prescaler 104 divides the output frequency Fout by a certain ratio to generate the low-frequency signal f(div). The division ratio is typically variable to permit rapid changes in the synthesized frequency. In this embodiment of frequency synthesizer 100, an overflow bit “of”, which is generated by an accumulator 105, can control the modulus of prescaler 104. Thus, the synthesized frequency can be computed using the following equation:Fout=(N+n)×Fref 
FIG. 2A illustrates an exemplary prescaler 104 including a dual-modulus. Specifically, in prescaler 104, a differential input signal, i.e. Fin and Fin(bar), is received by a full speed divide-by-2 block 201. The output signal of divide-by-two block 201, i.e. F2 and F2(bar), is provided to a half-speed divide-by-two block 202. For dual-modulus operation, divide-by-2 block 202 is implemented using a master-slave configuration that generates four signals: F4I, F4Q, F4I(bar), and F4Q(bar).
Frequency control block 205 generates a control signal 206 that determines the operation of phase select block 203. Specifically, if frequency control block 205 is disabled, then control signal 206 directs phase select block 203 to choose one of signals F4I, F4Q, F4I(bar), and F4Q(bar) and provide that signal to a low-speed divide-by-32 block 204. In this case, the resulting output frequency Fout would be 2×2×32=128 times smaller than input frequency Fin.
However, if frequency control block 205 is enabled, then control signal 206 directs phase select block 203 to choose a different phase for every positive edge of output signal Fout. Specifically, phase select block 203 will select the signal that is 90 degrees delayed with respect to the present signal. In one embodiment, F4I is initially selected and therefore is associated with 0 degrees, F4Q is then associated with 90 degrees, F4I(bar) is associated with 180 degrees, and F4Q(bar) is associated with 270 degrees. Because each subsequent signal lags the present signal by 90 degrees, signal F4 will be delayed accordingly.
FIG. 2B illustrates an exemplary phase select block 203 that includes two selection stages. In a first stage, the in-phase (I) and quadrature (Q) signals can be amplified by differential-to-single-ended amplifiers 210 and 211. Amplifiers 210 and 211 can be switched between positive and negative amplification using control signals 206A and 206B, respectively. A logic gate block 214 (in this embodiment including an inverter and NAND gates), using a control signal 206C, can determine which of the signals is actually output as signal F4. Thus, control signal 206 (FIG. 2A) can be implemented using control signals 206A, 206B, and 206C (FIG. 2B).
Notably, a sudden selection of a different signal phase may result in the creation of discontinuities in signal Fout that can result in a miscount by a divider circuit clocked by the selected phase. A gradual shift from one phase to the next may serve to avoid this genreation of errors in a divider circuit.
Therefore, a need arises for a phase selector that can shift phases gradually rather than substantially instantaneously.